1. Field
This invention relates generally to charge trapping layers for electronic memory devices and, more particularly, to complex oxide nanodots and methods for forming complex oxide nanodots.
2. Description of the Related Art
The sizes of features in semiconductor memory devices are constantly being scaled down to fulfill demands for diminishing device sizes and increased memory capacity. Nonvolatile storage devices such as Flash, ROM, NROM, and other magnetic and optical disk drives are encountering scaling challenges. For example, the vertical scaling of floating gate transistors for Flash memory devices has been difficult due to problems such as charge retention failures, inter-floating gate coupling, and stress induced leakage current (SILC) losses caused by defects in the gate oxide.
As scaling has progressed, various technologies have been developed. For example, nonvolatile memory technology has used ONO (SiO2/SiN/SiO2) stacks for inter-poly dielectric layers. However, ONO stacks thinner than 13.0 nm can encounter charge retention failures and threshold voltage instability in some circumstances. Replacing ONO stacks with SONOS (Si/SiO2/SiN/SiO2/Si) dielectric layers has been one approach to realize vertical scaling for nonvolatile memory devices. The increase in programming speed and lower voltage operation provided by SONOS devices has been enabled by reducing the tunneling dielectric layer thickness. However, reducing the tunneling dielectric layer thickness can seriously degrade the charge retention capability of the device. Thus, conventional SONOS has shown intrinsically poor charge retention properties for very thin tunneling oxides of about 2 nm thick or less. The use of thicker tunneling oxides has been impractical due to parasitic gate erase currents.
Thus, there is a continuing need for new nonvolatile memory technologies.